Many electronic devices and systems have the capability to store and retrieve information in a memory structure. A number of different memory structures are used in such systems. One prominent volatile memory is a DRAM structure that allows for high speed and high capacity data storage. Some examples of non-volatile memory structures include ROM, ferroelectric structures (e.g., FeRAM and FeFET devices) and MRAM structures.
With regard to ferroelectric (FE) structure, these structures can be in the form of a capacitor (e.g., a FeRAM) or a transistor (FeFET), where information can be stored as a certain polarization state of the ferroelectric material within the structure. The ferroelectric material that can be used is hafnium dioxide or zirconium dioxide or a solid solution of both transition metal oxides. In the case of pure hafnium oxide, the remanent polarization can be improved by a certain amount of dopant species has to be incorporated into the HfO2 layer during the deposition.
The ferroelectric material is intended to partially or fully replace the gate oxide of a transistor or the dielectric of a capacitor. The switching is caused by applying an electrical field via voltage between transistor gate and transistor channel. Specially, for n-channel transistors, ferroelectric switching after application of a sufficiently high positive voltage pulse causes a shift of the threshold voltage to lower or negative threshold voltage values. For p-channel transistors a negative voltage pulse causes a shift of the threshold voltage to higher or positive threshold voltage values.
A problem that can occur is that minority carrier trapping from the channel region can shift the threshold voltage of transistors oppositely to the direction caused by ferroelectric switching. Accordingly, it is desirable to avoid charge trapping for a ferroelectric non-volatile memory device. Other negative impacts of trapping are increased leakage current and earlier breakdown of the ferroelectric/interfacial layer causing a reduced lifetime of the ferroelectric transistor or capacitor. In order to do this, the ferroelectric properties of the ferroelectric material must be improved to improve the lifetime of the ferroelectric device.
However, even with improvements to the ferroelectric properties, charge trapping within the ferroelectric layer cannot be avoided completely. For example, due to the ability to make HfO2 thin together with a very thin interface layer while still maintaining its ferroelectric properties (low dead layer effect), charge trapping becomes much more critical compared to other ferroelectric materials such as PZT or SBT. For PZT or SBT materials, a layer thickness must be about 100 nm combined with a thick interface layer used as barrier which in turn renders charge trapping less critical or prevents it completely. To improve the sensing (the same as reading) and memory window of the device with thin ferroelectric materials, electrical de-trapping can be carried out by applying an additional voltage pulse. The voltage pulse, while unloading the traps, should however not disturb the ferroelectric state of the gate material.
Thus, it is desirable to minimize charge trapping such that the polarization state of the FE material is not adversely affected.